Telco Testing Solutions

Mixed Signal Tester “MiST”
	System
	Architecture	Multiple processor
	Master Clock	400Mhz, <50 psec jitter
	DDS Clock (16 each)	0.23Hz - 10MHz, 0.23Hz r
	User program language	GUI Test Programming Language
	Operating System	Windows 2000 / XP
	Bus Speed	25Mhz (Zero Wait state)

	Tester Board Set
	Pin Electronics Board	64 digital pins with 4 VI source
	VI Board	24 analog pin @ +/-100V, 0.5Amp
	Power VI Board	8 power analog pin @ 65V, 20Amp
	T/D Converter (TFE)	1

	System
	Support Interfaces	IEEE488, E1149.1 JTAG Bus
	Handler Interface	Parallel

	Physical
	Weight	575 lbs
	Height	50 inches
	Width	42 inches

	Depth	26 inches