Telco Testing Solutions

Mixed Signal Tester Expansion Cells “MiSTEC”
	System
	Architecture	Multiple processor
	Master Clock	400Mhz, <50 psec jitter
	DDS Clock (16 each)	0.23Hz - 10MHz, 0.23Hz r
	User program language	GUI Test Programming Language
	Operating System	Windows 2000 / XP
	Bus Speed	25Mhz (Zero Wait state)

	Resources
	Pin Electronics	64 digital pins with 4 VI source
	VI	6 analog pin @ +/-40V, 0.5Amp
	T/D Converter (TFE)	1

	System
	Support Interfaces	IEEE488, E1149.1 JTAG Bus
	Handler Interface	Parallel

	Physical
	Weight	200 lbs (100 lbs/cell) (45.6 kg/cell)
	Height	18.75 inches (476.3 mm)
	Width	19.00 inches (241.3 mm)

	Depth	27.5 inches (698.5 mm)